1. Technical Field of the Invention
The present disclosure relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device having a multiple gate insulating layer.
2. Description of the Related Art
Certain products in the semiconductor industry require semiconductor devices having various properties. To accommodate these types of products, system-on-chip (SOC) technology which merges a memory and a logic circuit into one chip has been developed. For example, an MDL (merged DRAM and Logic) device in which a dynamic random access memory (DRAM) region and a logic region are merged, and an MFL (merged Flash and Logic) device in which a flash memory region and a logic region are merged, have each been developed given as typical example.
To fabricate devices having various properties, such as, different operating voltages in a single chip, gate insulating layers should be formed having various thicknesses. For example, with a MDL device, a high voltage is applied to a gate insulating layer in the DRAM region, so that the gate insulating layer should be formed relatively thick in this region, whereas, in the logic region which may require a fast operating speed, the gate insulating layer in this region should be formed relatively thin. Moreover, even with a chip composed of the same devices, the devices of this chip should still have gate insulating layers with various thicknesses so that different operating voltages may be applied thereto. For example, a negative channel metal oxide semiconductor (NMOS) region should have a thicker gate insulating layer than a positive channel metal oxide semiconductor (PMOS) region, and a peripheral region should have a thicker gate insulating layer than a cell region.
Consequently, techniques of forming dual or multiple gate insulating layers having different thicknesses on a semiconductor substrate have been developed.
For example, a method of forming a dual gate insulating layer is described in U.S. Pat. No. 6,124,171, entitled “Method of Forming Gate Oxide Layer Having Dual Thickness by Oxidation Process.” According to U.S. Pat. No. 6,124,171, after growing a first gate oxide layer on a semiconductor substrate, a silicon nitride layer pattern is formed on the first gate oxide layer. The first gate oxide layer is etched using the silicon nitride layer pattern as an etching mask. Subsequently, a second gate oxide layer that is thinner than the first gate oxide layer is grown on the exposed surface of the semiconductor substrate.
However, the above-mentioned conventional method may have difficulties with respect to forming gate insulating layers having different thicknesses in, for example, three or more different regions, because in this conventional method a second gate oxide layer is grown by performing an oxidation process again after etching and removing the first gate oxide layer. Furthermore, another difficulty with the above conventional method may be that by forming a thin gate oxide layer in a PMOS region, boron implanted in a polysilicon gate may penetrate into a channel region through a gate oxide layer and cause polysilicon gate depletion and threshold voltage fluctuation.
Thus, there is a need for a method of fabricating a semiconductor device having gate insulating layers with different thicknesses formed on a semiconductor substrate using a single oxidation process. In addition, there is a need for a method of fabricating a semiconductor device which can minimize polysilicon gate depletion and threshold voltage fluctuation caused by impurities penetrating from a gate electrode to a channel region.